This invention relates to semiconductor devices, and more particularly to an electrically programmable memory cell of the floating gate type which is especially adapted for use in a fault-tolerant dynamic RAM.
As the bit density increased in MOS/LSI dynamic memory devices, the possibility of obtaining acceptable yields of good electrical bars per slice decreases. A 64K bit dynamic RAM may be manufactured efficiently at low cost, but perhaps a 256K bit device cannot. For this reason, various methods of rendering the devices "fault tolerant" have been devised. Typically, redundant cells are included, and some mechanism is provided for substituting the redundant cells when bad cells are addressed. Various circuits for performing this substitution are set forth in U.S. Pat. Nos. 4,051,354 and 4,047,163, issued to Wm. C. Choate et al and assigned to Texas Instruments. Fault tolerant memory devices of this type may employ electrically programmable memory (EPROM) cells on the dynamic memory chip to store the addresses of bad cells or rows with bad cells. The EPROM cells most widely manufactured today are of the double level polysilicon floating gate type such as shown in U.S. Pat. No. 3,984,822 issued to Simko et al. The process used to make these devices is not sufficiently compatible with the process used to make typical dynamic RAMs, because the EPROM needs implants after first level poly and before second level poly to make connection to source/drain diffused regions.
It is the principal object of this invention to provide a method of making EPROM cells which is compatible with a standard process for making dynamic RAM cells. Another object is to provide an improved method of making fault tolerant memory devices. A further object is to provide an improved electrically programmable memory device.